3.0 ps switching operation in all-Nb Josephson logic gates

12 February 1987

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 23 (4) , 163-165
https://doi.org/10.1049/el:19870116

Abstract

A high-speed logic delay of 3.0 ps/gate in a resistor-coupled Josephson logic (RCL) gate chain is attained using a new Nb Josephson integrated circuit technology. Lift-off, Nb stress control and planarisation techniques are used for fabricating high-quality Nb/AlO_x/Nb trilayer junctions and reliable Nb wiring. Pd, which is stable during etching, is used as a resistor material.

Keywords

3 PS
JOSEPHSON INTEGRATED CIRCUIT TECHNOLOGY
TRILAYER JUNCTIONS
NB-ALOX-NB
LIFTOFF
STRESS CONTROL
RESISTOR-COUPLED JOSEPHSON LOGIC
JOSEPHSON LOGIC GATES
HIGH-SPEED LOGIC DELAY
PLANARISATION TECHNIQUES
SWITCHING OPERATION

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