Using a visual formalism for design verification in industrial environments
- 1 January 1998
- book chapter
- Published by Springer Nature
- p. 208-221
- https://doi.org/10.1007/bfb0053507
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- A graphical environment for the design of concurrent real-time systemsACM Transactions on Software Engineering and Methodology, 1997
- Graphical specification and reasoning: Case study generalised railroad crossingPublished by Springer Nature ,1997
- Containment of regular languages in non-regular timing diagram languages is decidablePublished by Springer Nature ,1997
- A visual formalism for real time requirement specificationsPublished by Springer Nature ,1997
- The Real-Time Graphical Interval Logic toolsetPublished by Springer Nature ,1996
- Graphical formalization of real-time requirementsPublished by Springer Nature ,1996
- Symbolic Boolean manipulation with ordered binary-decision diagramsACM Computing Surveys, 1992
- Sequential circuit verification using symbolic model checkingPublished by Association for Computing Machinery (ACM) ,1990
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Automatic verification of finite state concurrent system using temporal logic specificationsPublished by Association for Computing Machinery (ACM) ,1983