Bounded delay timing analysis of a class of CSP programs with choice
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Using partial orders to improve automatic verification methodsPublished by Springer Nature ,2005
- Algorithms for interface timing verificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Practical applications of an efficient time separation of events algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An algorithm for exact bounds on the time separation of events in concurrent systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis of timed asynchronous circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
- Trace Algebra for Automatic Verification of Real-Time Concurrent SystemsPublished by Defense Technical Information Center (DTIC) ,1992
- Verifying automata specifications of probabilistic real-time systemsPublished by Springer Nature ,1992
- Modular Construction and Partial Order Semantics of Petri NetsPublished by Springer Nature ,1992
- Basic notions of trace theoryPublished by Springer Nature ,1989
- COSY: Its relation to nets and to CSPPublished by Springer Nature ,1987