A 2 GS/s 6 b ADC in 0.18 μm CMOS
- 22 December 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1 (01936530) , 322-497
- https://doi.org/10.1109/isscc.2003.1234317
Abstract
A 2 GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18 /spl mu/m CMOS. Three cross-connected and pre-distorted reference voltages improve the averaging performance. Circuit techniques enabling an SNDR of 30 dB at Nyquist input frequency and a FOM of 3.5 pJ per conversion step are discussed, and experimental results validating the simulated performance metrics are presented.Keywords
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