A new technique to minimize the EPROM cell

1 January 1978

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 181-184
https://doi.org/10.1109/iedm.1978.189382

Abstract

This paper presents a new technique to minimize the UV Erasable, Electrically Programmable, Read-Only Memory (EPROM) cell based on N-channel double polysilicon gate MOS. The new technique features a fully self-aligned floating gate structure which reduces the EPROM cell size/bit to almost that of presently most advanced mask ROMs. A new fabrication process and the experimental results for both programming and erasure are presented. The dependence of characteristics on various device parameters are discussed with emphasis on the difference from conventional devices.

Keywords

EPROM
NONVOLATILE MEMORY
READ ONLY MEMORY
FABRICATION
OXIDATION
THRESHOLD VOLTAGE
DIELECTRICS AND ELECTRICAL INSULATION
ELECTRON EMISSION
THICKNESS CONTROL
SILICON

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