A new floorplanning method with global routing based on functional partitioning

Publisher Website

6 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iscas.1988.15261

Abstract

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Keywords

This publication has 1 reference indexed in Scilit:

CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985