Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In sub-half micron CMOS, reduction of wiring capacitance is a key issue to improve the circuit performance because the ratio of wiring delay to total delay is increasing. In order to reduce the wiring capacitance, applying low dielectric materials to ULSI is most effective and developments of low dielectric materials have been reported recently. However, there have been no studies of applying those to sub-half micron CMOS. In this study, it is reported for the first time that the new low dielectric material "SiOF" which has been proposed previously has been applied to sub-half micron CMOS and the improvement of circuit performance has been confirmed. Moreover, it is clearly demonstrated that the SiOF film is inevitable to improve the circuit speed of 0.35 /spl mu/m CMOS with the scaling trend. Also, it is emphasized that the reduction of wiring capacitance with SiOF film is important from the viewpoint of power reduction in sub-half micron CMOS.<>Keywords
This publication has 1 reference indexed in Scilit:
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