High-Speed E/D GaAs ICs with Closely-Spaced FET Electrodes

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Abstract
In order to realize excellent performance on E/D GaAs ICs, the basic MESFET structure and the performance dependence on device geometry were experimentally investigated. By adopting closely-spaced electrode FET structure and by reducing the gate length, high-speed, low-power ICs could be fabricated. A 37.2 ps propagation delay (t pd) with very low power dissipation (P d) of 261 µW and a 34.1 ps minimum (t pd) were obtained from a 15-stage ring oscillator with 0.4 µm-long gate FETs. In a binary frequency divider with 0.5 µm-long gate FETs, a 2.2 GHz maximum clock frequency (f C) and a 1.6 GHzf C at 1.0 V drain bias with 228 µW/gate P d were achieved.

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