CMOS logic circuit optimum design for radiation tolerance

10 November 1983

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 19 (23) , 977-979
https://doi.org/10.1049/el:19830664

Abstract

CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR.

Keywords

RADIATION EFFECTS
THREE-INPUT NAND
RADIATION TOLERANCE
TRANSISTOR PARAMETER SHIFT DATA
CMOS LOGIC CIRCUIT
THREE-INPUT NOR
GATE AREA
OPTIMUM DESIGN
DC NOISE IMMUNITY

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