A fault diagnosis algorithm for asymmetric modular architectures

• 1 January 1981
• journal article
• Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
• Vol. C-30  (1) , 81-83
• https://doi.org/10.1109/TC.1981.6312161

Abstract

Keywords

• FAULT DIAGNOSIS
• ALGORITHM DESIGN AND ANALYSIS
• LOGIC GATES
• PARTITIONING ALGORITHMS
• TESTING
• CIRCUIT FAULTS
• COMPUTER ARCHITECTURE