Process modeling for submicron complementary metal-oxide-semiconductor very large scale integrated circuits

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Abstract
The issues arising in process modeling of submicron complementary metal-oxide semiconductor (CMOS) very large scale integrated circuits (VLSI) are examined for technologies with minimum feature sizes as small as 1/4 μm. The current process models, simulation methods, and existing process simulators are reviewed. Feature size reduction by a factor of about 5, increase of the dimensionality from one/two to two/three, enchanced process step coupling, new nonequilibrium processing methods, and the lack of multidimensional characterization methods are identified as the most important issues for process modeling. Two complementary paths for the evolution of process modeling are suggested.

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