Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/)

Publisher Website

1 January 1997

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 149-150
https://doi.org/10.1109/vlsit.1997.623742

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

CMOS scaling into the 21st century: 0.1 µm and beyond
IBM Journal of Research and Development, 1995
Self-Consistent Results for $n$ -Type Si Inversion Layers
Physical Review B, 1972