On uniform one-chip VLSI design considerations for some discrete orthogonal transforms
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 2136-2139 vol.4
- https://doi.org/10.1109/icassp.1988.197054
Abstract
One-chip VLSI design consideration for AT/sup 2/ optimal fast Fourier transform (FFT) shuffle-exchange architecture is considered, and a systolic-network architecture for the computation of the FFT is presented. This architecture has the same asymptotically optimal theoretical O(N/sup 2/log/sup 2/N) AT/sup 2/ complexity as the FFT shuffle-exchange architecture, but is more suitable for one-chip VLSI design. Architectures which are feasible for a one-chip FFT design, as well as for shuffle-exchange-type fast discrete orthogonal transforms such as the generalized transform, cosine transform, and slant transform are also discussed.<>Keywords
This publication has 6 references indexed in Scilit:
- An optimized VLSI architecture for a multiformat discrete cosine transformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A Discrete Fourier-Cosine Transform ChipIEEE Journal on Selected Areas in Communications, 1986
- Fourier Transforms in VLSIIEEE Transactions on Computers, 1983
- Two VLSI Structures for the Discrete Fourier TransformIEEE Transactions on Computers, 1983
- Why systolic architectures?Computer, 1982
- A fast cosine transform in one and two dimensionsIEEE Transactions on Acoustics, Speech, and Signal Processing, 1980