POSE

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Abstract
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and aca- demia with an environment and tool suite for automatic syn- thesis and optimization of low power circuits. POSE provides a unified framework for specifying and maintaining power rel- evant circuit information and means of estimating power con- sumption of a circuit using different load models. POSE also gives a set of options for making are-power trade-offs during logic optimization. 1. Introduction In the past, the main objective of designers has been to design faster and denser circuits. In response to this demand, design tools have been developed to help automate the design process for achieving maximum speed and minimum area. These design automation tools have been used extensively in the industry and are an integral part of any design cycle. With the increased popularity of portable devices, battery size and lifetime are becoming important factors in the design process. At the same time, the amount of data to be processed is increasing at a rapid pace. This also calls for faster digital devices which in turn increases power consumption. The cir- cuit power is also becoming one of the limiting factors in the amount of logic that can be placed in a VLSI chip and the determining factor in the packaging cost. These consider- ations have resulted in a growing need for minimizing power consumption in today's digital systems. The demand for low power digital systems has motivated significant research in the area of power estimation and power optimization. Power estimation and optimization techniques have been proposed at all stages of the design process. Power estimation techniques have been proposed by researchers at the gate level (3), (8), (15), (17), (21). Power optimization techniques have also been proposed at all levels of the design abstraction. Many optimization approaches have been pro- posed at the behavioral, RT and logic level (2), (5), (9), (10), (16), (19), (20). Reference (18) contains a detailed survey. Even though considerable effort has been made in creat- ing new techniques for power estimation and optimization, a unified framework for designing low power digital systems has not yet been developed. The void created by the absence of such a framework has presented designers with serious problems. Optimization algorithms that target low power cir- cuits use the frameworks designed for synthesizing minimum

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