Stress-induced double-hump substrate current in MOSFET's

1 December 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 7 (12) , 664-666
https://doi.org/10.1109/edl.1986.26512

Abstract

Asymmetries in substrate current characteristics due to hot-electron stressing have been observed in short-channel n-MOSFET's. Due to the localized nature of trapped charges or interface traps as a result of hot-electron stressing, transistors can show single-peak or double-hump substrate current characteristics under normal- or reverse-mode measurements. Two-dimensional simulations indicate that a high lateral electric field is generated near the source when the negative charges are trapped there. This electric field is responsible for the observed double-hump substrate current and enhanced gate current injection under reverse-mode measurements for the stressed transistors.

Keywords

This publication has 0 references indexed in Scilit: