Breakdown voltage design considerations in VDMOS structures
- 1 January 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 31 (1) , 109-113
- https://doi.org/10.1109/t-ed.1984.21483
Abstract
Analytical closed-form expressions for the breakdown voltage in punched-through VDMOS structures, including the effect of floating guardrings and field plates, are derived in this paper. The theoretical results are confirmed by measured data on VDMOS devices, as well as on floating-guardring diode test structures, fabricated on n/n+epitaxial substrates.Keywords
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