An optimized reconfigurable architecture for transputer networks

Abstract
This paper presents the architecture of a fully reconfigurable distributed memory computing system. It is assumed that the processors communicate via message passing on an application specific regular network of degree four. To realize any network of this class, they use a special multistage Clos network which is built up by a minimal number of equal sized switches. These switches can be configured to realize any connection between input and output ports. To map a network onto the architecture, the process graph has to be partitioned into a number of subsets. The authors prove that the number of external edges between the subsets can be bounded. For that reason, it is possible to minimize the number of links and switches in the architecture without losing the ability to realize any regular network of degree four. Moreover, any user specific network can be mapped efficiently on the architecture. The practical relevance of this work was shown by the realization of the architecture by Parsytec. Their largest system has 320 processors.

This publication has 12 references indexed in Scilit: