A scalable SOI technology for three successive generations: 0.18, 0.13 and 0.1 μm for low-voltage and low-power applications
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 1078621X,p. 118-119
- https://doi.org/10.1109/soi.1996.552522
Abstract
Optimized 0.18 /spl mu/m gate length NMOSFET and PMOSFET SOI devices have been demonstrated with high electrical performances for low-voltage and low-power applications. The electrical results show that this SOI design can be easily scaled down for the next generations and no heavy ion implant (In or Sb) is required.Keywords
This publication has 1 reference indexed in Scilit:
- A room temperature 0.1 μm CMOS on SOIIEEE Transactions on Electron Devices, 1994