A General Etching Simulator for VLSI Lithography and Etching Processes: Part II - Application to Deposition and Etching
- 1 August 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (4) , 520-524
- https://doi.org/10.1109/jssc.1980.1051432
Abstract
The extension of the general process simulator SAMPLE to plasma etching and metallization is described. The etching algorithm is divided into isotropic, anisotropic, and direct milling components and is suitable for modeling wet etching, plasma etching, reactive ion etching, and ion milling. Separate deposition algorithms are used for CVD, sputtering, and planetary deposition. With the extension, it is possible to use a simple keyword repertoire to simulate a sequence of photo-lithography, etching, and deposition steps to obtain device cross sections at each stage of fabrication.Keywords
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