Reversible and irreversible trapping at room temperature in poly(thiophene) thin-film transistors

Preprint

28 February 2005

preprint
Published by arXiv in arXiv

https://doi.org/10.48550/arXiv.cond-mat/0502642

Abstract

We measured the bias stress characteristics of poly(thiophene) semi-crystalline thin-film transistors (TFTs) as a function stress times, gate voltages and duty-cycles. At room temperature, the bias stress has two components: a fast reversible component and a slow irreversible component. We hypothesize that the irreversible component is due to charge trapping in the disordered areas of the semiconductor film. At low duty-cycle (<2%), the fast bias stress component is reversed during the off-part of the cycle therefore the observed VT shift in only caused by irreversible trapping. Irreversible trapping follows power-law kinetics with a time exponent approximately equal to 0.37. We use these findings to estimate the lifetime of TFTs used as switches in display backplanes.

Keywords

All Related Versions

Version 1, 2005-02-28, ArXiv
Published version: Applied Physics Letters, 86 (26).

This publication has 0 references indexed in Scilit: