Stanford Telecom VLSI design of a convolutional decoder

13 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 171-178 vol.1
https://doi.org/10.1109/milcom.1989.103920

Abstract

The authors describe the novel hardware and speed-efficient architectural features of a recent Stanford Telecom VLSI implementation of a 20-Mb/s convolutional decoder using 1.5- mu m CMOS technology. The chip offers a selection of convolutional codes, including the

Keywords

TELECOMMUNICATIONS
VERY LARGE SCALE INTEGRATION
DECODING
CONVOLUTIONAL CODES
CMOS TECHNOLOGY
TIME DIVISION MULTIPLE ACCESS
READ-WRITE MEMORY
HARDWARE
SATELLITE COMMUNICATION
LOGIC