Comparison of buffering strategies for asymmetric packet switch modules

Abstract
The performance of a class of asymmetric packet switch modules with channel grouping is analyzed. The switch module considered has n inputs and m outputs. A packet destined for a particular output address (out of g) needs to access only one of the r available physical output ports: m=gr. These switch modules are the key building blocks in many large multistage switch architectures. The focus is on the performance of input-buffered and output-buffered switch modules under geometrically bursty traffic. A combination of exact derivation, numerical analysis, and simulation yields the saturation throughput of input-buffered switch modules and the mean delay of the input-buffered and output-buffered switch modules. Tables and formulas useful for traffic engineering are presented. The results show that increasing the number of output ports per output address (r) can significantly improve switch performance, especially when traffic is bursty. Although output-buffered switch modules have significantly better performance than input-buffered switch modules when there are equal numbers of input and output ports, this performance difference becomes significantly smaller when the switch dimensions are asymmetric

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