Process and performance comparison of an 8K × 8-bit SRAM in three stacked CMOS technologies

1 October 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 6 (10) , 548-550
https://doi.org/10.1109/EDL.1985.26225

Abstract

Using self-aligned and non-self-aligned stacked CMOS technologies experimental 8K × 8-bit static random-access memories (SRAM'S) have been fabricated. Hydrogen passivation has been used to improve the performance of polysilicon devices. An 8K × 8-bit SRAM using non-self-aligned memory cells and employing a CW argon laser to anneal the second (active) polysilicon layer has also been fabricated. The fabrication methods and performances of all three SRAM's have been compared.

Keywords

CMOS TECHNOLOGY
RANDOM ACCESS MEMORY
CMOS PROCESS
GEOMETRY
PASSIVATION
ANNEALING
IMPLANTS
HYDROGEN
THRESHOLD VOLTAGE
BORON

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