Using VHDL for simulation of SDL specifications
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors present the use of VHSIC hardware description language (VHDL) for the simulation of Specification and Description Language (SDL) specification. SDL is a standardized graphical specification and description language. It is widely used for specifications of software systems that are based on message exchange, e.g., telecommunication systems. The approach presented allows for simulation of the logical correctness of the specification, as well as some kinds of performance simulation. A third application of the approach is the joint simulation of hardware and software. The translation of SDL into VHDL allows for functional, performance, and joint hardware/software simulation of systems specified with SDL.Keywords
This publication has 5 references indexed in Scilit:
- Structured analysis and VHDL in embedded ASIC design and verificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Translating system specifications to VHDLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- SpecCharts : A Language for System Level SynthesisPublished by Elsevier ,1991
- Rationale and tutorial on OSDL: An object-oriented extension of SDLComputer Networks and ISDN Systems, 1987
- Statecharts: a visual formalism for complex systemsScience of Computer Programming, 1987