A high density 4M DRAM process using folded bitline adaptive side-wall isolated capacitor (FASIC) cell

1 January 1986

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 144-147
https://doi.org/10.1109/iedm.1986.191134

Abstract

Submicron CMOS process technologies for a high density 4M DRAM are presented emphasizing a cell area reduction to 10.9 um2 using a newly proposed FASIC cell. Two novel techniques were developed to realize the new cell structure. The oblique ion implantation technique can make a shallow impurity doping into the side wall and the local oxidation at the side wall technique makes the half-contact/cell architecture on the peripheral trench type cell.

Keywords

RANDOM ACCESS MEMORY
CAPACITORS
OXIDATION
ETCHING
CMOS TECHNOLOGY
DIELECTRIC FILMS
RESISTS
ISOLATION TECHNOLOGY
ION IMPLANTATION
IMPURITIES

This publication has 0 references indexed in Scilit: