Performance evaluation of parallel concatenated codes
- 1 January 1995
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 663-667
- https://doi.org/10.1109/icc.1995.524187
Abstract
A parallel concatenated coding scheme consists of two simple systematic constituent encoders linked by an interleaver. The input bits to the first encoder are scrambled by the interleaver before entering the second encoder. The codeword of the parallel concatenated code consists of the input bits followed by the parity check bits of both encoders. The authors propose a method to evaluate the bit error probability of a parallel concatenated coding scheme in a way which is independent from the interleaver used. The two cases of parallel concatenated block codes and parallel concatenated convolutional codes are considered.Keywords
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