An efficient logic block interconnect architecture for user-reprogrammable gate array
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 31.3/1-31.3/4
- https://doi.org/10.1109/cicc.1990.124842
Abstract
A novel architecture for an SRAM-based user-reprogrammable gate array which consists of programmable logic elements (PLEs), switching stations (SSs), wirings, and input/output blocks (IOBs) is discussed. The SS is designed to connect its neighboring PLEs and/or IOBs through only one NMOS pass transistor to maintain a sufficient signal level and reduce the delay in signal propagation. Hidden interconnection networks which directly merge neighboring PLEs were adopted to expand the number of inputs and product terms of combinational logic, and allow the construction of a parallel-to-serial/serial-to-parallel converter without using SSs. A fabricated CMOS prototype chip includes an 8 Kbit 50 ns temporary storage memory which is programmable to the random access mode or the FIFO mode with a word length of 4 bit or 8 bit.<>Keywords
This publication has 1 reference indexed in Scilit:
- A 9000-gate user-programmable gate arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003