Automatic gate-level synthesis of speed-independent circuits
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates is presented. The synthesized circuits are speed-independent-that is, they work correctly regardless of individual gate delays. Synthesis results for a variety of specifications taken from industry and previously published examples are presented. The speed-independent circuits are compared with those non-speed-independent circuits synthesized using previously described algorithms, in which delay elements are added to remove circuit hazards. These synthesis results show that the new circuits are on average approximately 25% faster with an area penalty of only 15%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efficient circuits compared to those synthesized with timing constraints.Keywords
This publication has 3 references indexed in Scilit:
- Synthesis of timed asynchronous circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Semi-modularity and testability of speed-independent circuitsIntegration, 1992
- Algorithms for synthesis of hazard-free asynchronous circuitsPublished by Association for Computing Machinery (ACM) ,1991