11.6 Gbps 1:4 demultiplexer using double pulse doped quantum well GaAs/AlGaAs transistors

28 February 1991

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 27 (5) , 459-462
https://doi.org/10.1049/el:19910289

Abstract

An ultrahigh speed 4 bit demultiplexer circuit has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3 μm gate length. First results show a data rate of 11.6 Gbit/s and a power consumption of 165 mW at 0.85 V supply voltage, including four 50 Ω buffers.

Keywords

ENHANCEMENT TRANSISTORS
4 BITS
BUFFERS
POWER CONSUMPTION
RECESSED GATE PROCESS
0.85 V
0.3 MICRON
165 MW
ULTRAHIGH SPEED
DEMULTIPLEXER CIRCUIT
DEPLETION TRANSISTORS
DOUBLE PULSE DOPED QUANTUM WELL TRANSISTORS
GAAS-ALGAAS
11.6 GBIT/S
DATA RATE

This publication has 1 reference indexed in Scilit:

Extreme Low Power 1:4 Demultiplexer Using Double Delta Doped Quantum Well GaAs/AlGaAs Transistors
Published by Japan Society of Applied Physics ,1990