Design of the APIC: A high performance ATM host-network interface chip

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1, 179-187 vol.1
https://doi.org/10.1109/infcom.1995.515875

Abstract

We present the design of a high performance ATM host-network interface for multimedia workstations and servers. At Washington University, as part of an ARPA-sponsored gigabit local ATM testbed, we are building a prototype of this interface that can support a sustained aggregate bidirectional data rate of 2.4 Gbps. The centerpiece of our interface design is a custom chip called the APIC (ATM port interconnect controller). Multiple such chips can be interconnected to yield a desk-area network (DAN) which would serve as a high speed I/O interconnect for the host computer. This paper details the internal design of the APIC chip, and outlines some of its key features. Noteworthy among these are: connection caching, transmit pacing, cell batching, remote control, and support for AAL-0, AAL-5, multipoint, and loopback connections. We have chosen to defer to a later paper the details pertaining to several other features which provide support for zero-copy, improved interrupt handling, direct control of the chip from user-space, and efficient buffering and demultiplexing.

Keywords

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