Optimizing Replication, Communication, and Capacity Allocation in CMPs

This publication has 17 references indexed in Scilit:

• The implementation of the Itanium 2 microprocessor
  IEEE Journal of Solid-State Circuits, 2002
• The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor
  IEEE Journal of Solid-State Circuits, 2002
• The SPLASH-2 programs: characterization and methodological considerations
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
  Published by Association for Computing Machinery (ACM) ,2002
• Simics: A full system simulation platform
  Computer, 2002
• A low-overhead coherence solution for multiprocessors with private cache memories
  Published by Association for Computing Machinery (ACM) ,1998
• Generating representative Web workloads for network and server performance evaluation
  ACM SIGMETRICS Performance Evaluation Review, 1998
• Trends in shared memory multiprocessing
  Computer, 1997
• The case for a single-chip multiprocessor
  Published by Association for Computing Machinery (ACM) ,1996
• Comparative performance evaluation of cache-coherent NUMA and COMA architectures
  Published by Association for Computing Machinery (ACM) ,1992