Early resolution of address translation in cache design

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Abstract
The authors describe a synonym-resolution mechanism based on highly accurate real address-prediction methods prior to the completion of address generation. The prediction method uses the contents of the base registers and proper history tables. Such early resolution of translation information may allow a more efficient implementation of high-performance processors. Several techniques were developed and evaluated by trace-based simulations. The feasibility of achieving over 98% accuracy of prediction with reasonable approaches is demonstrated. Early resolution of translation information can be rather critical for certain high-performance processor designs. In practice, such results should be realized with careful design in order to effectively reduce the critical path for cache accessing.

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