Simulation-Free Estimation of Speed Degradation in NMOS Self-Testing Circuits for CAD Applications

Abstract

A method is presented for estimating the maximum operating speed of NMOS self-testing circuits designed using the BILBO technique. The unique feature of this method is that the speed estimation is based only on parameters of the original design (without built-in test logic) and parameters describing the BILBO modules. Thus, a computer-aided optimization of a self-testing structure with respect to area/speed criteria can be performed without the necessity of laying out multiple self-testing versions of the original design and running timing simulation on each one.

Keywords

CIRCUIT SIMULATION
DEGRADATION
MOS DEVICES
BUILT-IN SELF-TEST
DESIGN AUTOMATION
LOGIC DESIGN
LOGIC TESTING
DESIGN OPTIMIZATION
TIMING
COMPUTATIONAL MODELING

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