Heat Transfer & Thermal Stress Analysis of Plastic-Encapsulated ICs

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Abstract
Analytic approaches of thermal stress in plastic-encapslated ICs reliability have been studied using a simple, 2-dimensional model of the cross section of ICs by the finite-element method. To test the validity of the model, the actual stress within the silicon chip was measured using piezoresistive devices. The calculated stress in the silicon chip agreed with the experimental values. The stress distributions were changed by lead-frame properties. Package cracking, and delamination between the molding plastic and the lead-frame were qualitatively explained. We estimated the effect of the plastic properties on stress quantitatively. Furthermore, to test the validity of this model, the temperature change at the silicon chip was measured using the Vf temperature dependency of a diode. The calculated temperature change at the silicon chip agreed with the observed values. A very high temperature gradient was observed near the surface of the plastic immediately after solder dipping. The non-uniform temperature distributions produced different thermal stress distributions than those observed in the steady-state. This result indicated that rapid thermal shock could delaminate the plastic from the lead-frame. We believe that these results can guide the development of an optimum low-stress plastic.