Substrate current in N-channel and P-channel MOSFETs between 77K and 300K: Characterization and simulation

1 January 1985

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1985.191036

Abstract

Silicon is the material of choice for fabrication of high circuit density, low defect density and high speed integrated devices. CMOS technology provides the additional advantage of low power dissipation. Performance enhancement can be obtained by operating CMOS circuits at liquid nitrogen temperatures [1]. However, low temperature operation exacerbates the generation of substrate current by impact ionization, leading to potential device degradation [2]. This work characterizes the temperature behavior of the substrate current, and presents a model describing this behavior based on Shockley's lucky electron (LE) model [3]. For N-channel (P-channel) devices, the model is extended using a Maxwell-Boltzmann (MB) distribution of hot electron (hole) energies above (below) the conduction (valence) band minimum (maximum}. We implement the model in the 2-D device simulator CADDET [4]. The agreement between data and simulations enhances physical understanding of substrate current in MOSFETs, and warrants confident design of a CMOS technology for cryogenic operation.

Keywords

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