A new edge-defined approach for submicrometer MOSFET fabrication

1 January 1981

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 2 (1) , 4-6
https://doi.org/10.1109/edl.1981.25319

Abstract

A novel technique employing vertical (anisotropic) dry etching for fabricating edge-defined submicrometer MOSFETs is described, and preliminary results are presented. Three basic process techniques are employed: formation of an edge-defined submicrometer element, pattern transfer of the element into an underlying doped polysilicon gate layer, and passivation of the FET using a sidewall oxide. The submicrometer element formation technique is limited to linewidths in the 0.1 µm to 0.4 µm range. Characterization of MOSFETs, having physical channel lengths ∼0.1 µm to 0.15 µm and believed to be the world's smallest MOSFET's reported to date, is discussed.

Keywords

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