Some consequences of ion beam shadowing in CMOS source/drain formation

1 December 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 7 (12) , 677-679
https://doi.org/10.1109/edl.1986.26517

Abstract

Under certain circumstances the shadowing of CMOS source/drain (S/D) ion implants by the gate material has been shown to lead to degradation of n-channel transistor characteristics. The orientation of the wafer with respect to the ion beam and the simultaneous diffusion of boron and phosphorus are key elements in explaining these experimental results. Two-dimensional simulations agree with experiment.

Keywords

ION BEAMS
SHADOW MAPPING
IMPLANTS
TESTING
BORON
SILICON
CMOS PROCESS
ELECTROSTATICS
DEGRADATION
ION IMPLANTATION

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