2 Micron merged bipolar-CMOS technology
- 1 January 1984
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 761-764
- https://doi.org/10.1109/iedm.1984.190837
Abstract
A 2 µm process, merging the major technologies required to fabricate VLSI MOS and bipolar transistors on the same integrated circuit, is described. Two mask steps are added to a two-layer metal N-well silicided CMOS process to fabricate the walled-polysilicon emitter NPN transistors. The non-epitaxial process was used to establish the current drive advantage gained by integrating NPN transistors with CMOS. By adding a 1 µm epitaxial layer and adopting a retrograde P-well, latchup is eliminated and VLSI bipolar performance becomes feasible.This publication has 0 references indexed in Scilit: