Using VHDL for Link to Synthesis Tools

Abstract

This paper presents the work done to use industry and academic synthesis tools for the hardware-software codesign of reactive systems. It emphhizes the hardware synthesis and design part by linking SIGNAL and VHDL. The SIGNAL language is used for system specification and VHDL for the link to synthesis tools. To permit a maximum of flexibility, different strategies for linking are described.

Keywords

SIGNAL SYNTHESIS
SIGNAL DESIGN
COMPUTER AIDED ENGINEERING
SIGNAL PROCESSING
DESIGN AUTOMATION
DELAY
HARDWARE
JOINING PROCESSES
SIGNAL GENERATORS
HIGH LEVEL SYNTHESIS

This publication has 3 references indexed in Scilit:

AMICAL: An interactive high level synthesis environment
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
High — Level Synthesis
Published by Springer Nature ,1992
Programming real-time applications with SIGNAL
Proceedings of the IEEE, 1991