Design of a MMIC low noise amplifier at 10 GHz

Publisher Website
Google Scholar
Abstract
In this paper the design of a MMIC low noise amplifier at 10 GHz is presented using Computer Aided Design (CAD) techniques. The foundry used for the fabrication of the chip is GEC-Marconi F20 process. This process has Ft=24 GHz and an associated gain of 10 dB with minimum noise figure of 1.6 dB at 12 GHz. The LNA is a two stage design where source peaking techniques have been used in order to have an acceptable level of unconditional stability in the whole frequency range from DC-20 GHz. The area of the chip is 2 mm/sup 2/, the two stage gain is 10 dB at 10 GHz, the noise figure obtained is almost 2 dB and the input and output return loss is better than 10 dB. The chip is designed to work in a low noise radar receiver. Experimental results are also measurements using a CASCADE wafer probe station concerning both linear (S-parameters, noise figure) and nonlinear measurements (power gain compression, spectrum). Very good agreement between theoretical and experimental results have been noticed due to the very good simulator used (MDS=Microwave Design System) as well as due to the very good smart libraries offered by GEC-Marconi.

This publication has 0 references indexed in Scilit: