An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 781-784
- https://doi.org/10.1109/iedm.1989.74170
Abstract
A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<>Keywords
This publication has 2 references indexed in Scilit:
- Design tradeoffs between surface and buried-channel FET'sIEEE Transactions on Electron Devices, 1985
- Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistorIEEE Transactions on Electron Devices, 1980