A 16×16-bit static CMOS wave-pipelined multiplier
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 4, 143-146
- https://doi.org/10.1109/iscas.1994.409217
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- Designing high-performance digital circuits using wave pipelining: algorithms and practical experiencesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Maximum-rate pipeline systemsPublished by Association for Computing Machinery (ACM) ,1969