A transceiver for 800 kb/s full-duplex transmission over digital subscriber loops using a custom VLSI adaptive filter processor
- 9 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 252-256
- https://doi.org/10.1109/vtsa.1991.246671
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
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- A 60-MHz 64-tap echo canceller/decision-feedback equalizer in 1.2- mu m CMOS for 2B1Q high bit-rate digital subscriber line transceiversPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing Recovery in Digital Synchronous Data ReceiversIEEE Transactions on Communications, 1976