A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter

1 June 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 21585601,p. 68-69
https://doi.org/10.1109/vlsic.2007.4342769

Abstract

A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670μm×350μm and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5dB and 35dB at 1.5GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.

Keywords

DIGITAL-ANALOG CONVERSION
CLOCKS
FREQUENCY SYNCHRONIZATION
BACKPLANES
MULTIPLEXING
CMOS PROCESS
POWER DISSIPATION
LINEARITY
DELAY LINES
ROUTING

This publication has 1 reference indexed in Scilit:

A 22GS/s 6b DAC with integrated digital ramp generator
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005