Signed-digit online floating-point arithmetic for FPGAs

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Abstract
Many potential applications for reconfigurable computing need the dynamic range provided by floating-point arithmetic. However, doing floating-point on FPGAs is difficult because of the large amount of hardware required, particularly for multipliers. Some limited success has been obtained through digit-serial implementation of IEEE floating-point multipliers, but the IEEE representation is not easily or efficiently implemented in serial form. Therefore, we have been exploring alternate number representations. Signed-digit representations have shown some promise, since their form lends them to serial computation, which consumes much less hardware than fully parallel approaches. We show how the signed-digit representation can be used to implement floating-point arithmetic, and we present prototype implementations using Altera FPGAs.

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