A one chip VLSI for real time two-dimensional discrete cosine transform
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 701-704
- https://doi.org/10.1109/iscas.1988.15022
Abstract
A single-chip two-dimensional discrete cosine transform processor is presented. This chip meets the challenge of high throughput rate (13.5 MHz) and versatility (block size from 4*4 to 16*16, and direct and inverse DCT) with a die area as small as 40 mm/sup 2/. An efficient optimized architecture providing high computation power is described. The chip is found to exhibit excellent precision performances. A full-custom approach was chosen because of the required speed and economic reasons (implementation of a low-cost real-time video coder/decoder). The chip uses a 1.25- mu m CMOS technology and contains 114000 transistors on 5.4*7.5 mm/sup 2/.Keywords
This publication has 5 references indexed in Scilit:
- An optimized VLSI architecture for a multiformat discrete cosine transformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A single chip video rate 16×16 discrete cosine transformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A Discrete Fourier-Cosine Transform ChipIEEE Journal on Selected Areas in Communications, 1986
- A two-dimensional fast cosine transformIEEE Transactions on Acoustics, Speech, and Signal Processing, 1985
- Discrete Cosine TransformIEEE Transactions on Computers, 1974