Application of temporal logic to the assistance of hardware logic design

1 January 1988

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 254-263
https://doi.org/10.1109/ismvl.1988.5182

Abstract

The specification of digital systems in temporal logic, a verification method between specification and gate-level designs, and a method for synthesizing state diagrams from specification are presented. Timing relations shown usually be timing diagrams can be described, and verification and synthesis can be done automatically. A hardware description language called Tokio, which is based on temporal logic and is an extension of Prolog, is also presented. The above techniques can be applied to Tokio.<>

Keywords

LOGIC DESIGN
TIMING
DIGITAL SYSTEMS
HARDWARE DESIGN LANGUAGES
SEQUENTIAL CIRCUITS
LABORATORIES
COMPUTATIONAL MODELING
VERY LARGE SCALE INTEGRATION
DELAY
PRODUCTION

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