Self-aligned transistor with sidewall base electrode

1 January 1981

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXIV, 214-215
https://doi.org/10.1109/isscc.1981.1156232

Abstract

This report will cover a multiple-self-aligned bipolar structure with negligible parasitic junction capacitances, suitable for scaled-down I²L-VLSI. A fabricated model indicared that CCBwas reduced by 75% and βuand βdwas increased 4 times compared to a conventional structure.

Keywords

ELECTRODES
EPITAXIAL LAYERS
FABRICATION
PARASITIC CAPACITANCE
BORON
ETCHING
SILICON
FREQUENCY
LABORATORIES
VERY LARGE SCALE INTEGRATION

This publication has 2 references indexed in Scilit:

Heavy doping effects in p-n-p bipolar transistors
IEEE Transactions on Electron Devices, 1980
A new polysilicon process for a bipolar device-PSA technology
IEEE Journal of Solid-State Circuits, 1979