Effects of film morphology and gate dielectric surface preparation on the electrical characteristics of organic-vapor-phase-deposited pentacene thin-film transistors

Organic vapor phase deposition was used to grow polycrystalline pentacene channel thin-film transistors. Substrate temperature, chamber pressure during film deposition, and growth rate were used to vary the crystalline grain size of pentacene films on ${\mathrm{O}}_2$ -plasma treated ${\mathrm{SiO}}_2$ from 0.2 to 5 μm, leading to room-temperature saturation regime field-effect hole mobilities ${\mathrm{(\mu }}_{\mathrm{eff}})$ from $\text{0.05±0.02}$ to $\text{0.5±0.1\hspace{0.17em}}{\mathrm{cm}}^2/\mathrm{V s},$ respectively. Surface treatment of ${\mathrm{SiO}}_2$ with octadecyltrichlorosilane (OTS) prior to pentacene deposition resulted in ${\mu }_{\mathrm{eff}}\text{⩽1.6\hspace{0.17em}}{\mathrm{cm}}^2/\mathrm{V s},$ and drain current on/off ratios of ${\text{⩽10}}^8$ at room temperature, while dramatically reducing the average grain size. X-ray diffraction studies indicate that the OTS treatment decreases the order of the molecular stacks. This suggests an increased density of flat-lying molecules, accompanying the improvement of the hole mobility at the pentacene/OTS interface.