Architecture of a 64-bit fuzzy inference processor
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1776-1780
- https://doi.org/10.1109/fuzzy.1994.343589
Abstract
The architecture of a 64-bit fuzzy inference processor (FIP) will be presented. A fuzzy system consisting of the FIP and a 64-bit microprocessor speeds-up the inference by up to 10 times. In addition we present an optimized inference algorithm which achieves a 50 fold acceleration for the calculation of the rule base. The FIP will be used only for the inference while the fuzzification and defuzzification will be done by the microprocessor (/spl mu/P), which will also do the controlling of the FIP. This results in a simple architecture and low hardware requirement. We use the min/max algorithm and an internal resolution of 8-bit. Up to 8 membership functions can be used for every input and output. A prototype (with 32-bit) was simulated on FPGA's and needed 180 ns for the calculation of one rule with 8 inputs and 2 outputs.Keywords
This publication has 3 references indexed in Scilit:
- RISC approach to design of fuzzy processor architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Architecture of a CMOS fuzzy logic controller with optimized memory organisation and operator designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A VLSI fuzzy logic controller with reconfigurable, cascadable architectureIEEE Journal of Solid-State Circuits, 1990